ASIC Design Verification Engineer, up to Sr. Staff
- qualcomm
- Taiwan, Taiwan
- TWD 2,000,000 – TWD 3,500,000
Company:
Qualcomm Semiconductor Limited
Job Area:
Engineering Group, Engineering Group > ASICS Engineering
General Summary:
Education
- MS/BS in EE (MS preferred)
Experience
- 2–15 years ASIC verification experience
- Experience in merchant silicon or switching ASIC (e.g., Broadcom, Marvell, Realtek, MTK networking chips) is desirable
Requirements
ASIC Verification
Familiar with ASIC development, especially ASIC verification using:
- System Verilog / UVM
- SVA
- Coverage-driven methodology
- Emulation / FPGA validation
Ethernet Networking Knowledge
Hands-on experience in Ethernet switching/networking ASICs, including:
Packet classification and forwarding pipelines
Buffer management and QoS mechanisms
Knowledge of protocols:
- Ethernet
- VLAN
- TCP/IP
- Tunneling
- TSN
- Other related networking protocols
Familiarity with Ethernet switching concepts, such as:
- L2/L3 forwarding
- Bridging and routing
- Packet processing pipelines
- Basic QoS (queuing and scheduling)
Technical & Soft Skills
- Strong debugging and system-level problem-solving skills
- Scripting skills (C/C++, Tcl, Perl) preferred
- Excellent teamwork, interpersonal, and communication skills
- Fluent in Chinese and English, both verbal and written
- Ability to work effectively under pressure and meet tight schedules
Description of Function & Responsibility
Verification Development
Develop testbench and test cases for Ethernet switch verification from:
- Module level
- Subsystem level
- System level
Cross-Functional Collaboration
Work with Architecture and Design teams on:
- Micro-architecture definition
- RTL design of networking blocks
- Test plan development
- Verification closure
Silicon Debug Support
Support Design and VI teams on:
- Pre-silicon debugging
- Post-silicon debugging
Team Development
- Mentor junior engineers and guide best engineering practices
Minimum Qualifications:
• Bachelor's degree in Science, Engineering, or related field and 6+ years of ASIC design, verification, validation, integration, or related work experience.
OR
Master's degree in Science, Engineering, or related field and 5+ years of ASIC design, verification, validation, integration, or related work experience.
OR
PhD in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience.
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Skills
- SystemVerilog
- UVM
- ASIC verification
- Ethernet Protocols
- FPGA validation
- C/C++
- Scripting (Tcl/Perl)








