Full Chip CAD Physical Design Engineer

Minimum qualifications:

• Bachelor's degree in Electrical Engineering, Computer Science, a related field, or equivalent practical experience.
• 10 years of experience in electronic design automation (EDA) tools and RTL2GDS flows.
• Experience in the semiconductor/EDA industry.

Preferred qualifications:

• Master’s degree in Computer Engineering/Electronics Engineering, or a related field.
• Experience with silicon quality or reliability.

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.The AI and Infrastructure team is redefining what’s possible. We empower Google customers with breakthrough capabilities and insights by delivering AI and Infrastructure at unparalleled scale, efficiency, reliability and velocity. Our customers include Googlers, Google Cloud customers, and billions of Google users worldwide.

We're the driving force behind Google's groundbreaking innovations, empowering the development of our cutting-edge AI models, delivering unparalleled computing power to global services, and providing the essential platforms that enable developers to build the future. From software to hardware our teams are shaping the future of world-leading hyperscale computing, with key teams working on the development of our TPUs, Vertex AI for Google Cloud, Google Global Networking, Data Center operations, systems research, and much more.

Responsibilities

• Demonstrate an understanding of the Register-Transfer Level (RTL) to Graphic Data Stream (GDS) II flow.
• Manage the implementation of large, complex system-on-chips (SoCs), subsystems, and sub-wrappers, and demonstrate an understanding of associated issues and solutions.
• Utilize floorplanning, power grid design, and place-and-route methodologies, and use Synopsys tools like Floorplan Compiler (FC) and Formality.
• Exhibit an understanding of advanced node design (e.g., 5nm and below) and related optimization techniques.
• Develop script in Synopsys TCL and Python.