Master Thesis Student – Compiler Optimization for RISC-V Processors

About GF

GlobalFoundries is a leading full-service semiconductor foundry providing a unique combination of design, development, and fabrication services to some of the world’s most inspired technology companies. With a global manufacturing footprint spanning three continents, GlobalFoundries makes possible the technologies and systems that transform industries and give customers the power to shape their markets. For more information, visit www.gf.com.

Introduction

We are looking for a highly motivated Master's Thesis Student to join our engineering team in Leuven, Belgium. This thesis project offers a unique opportunity to work at the intersection of advanced processor architectures and compiler technologies, contributing to the performance optimization of next-generation RISC-V processors. In this role, you will investigate the microarchitectural features of the RMX7xx, RHX1xx, and RPX1xx processor families and develop enhancements to the LLVM compiler framework to improve code generation efficiency and application performance. Your work will directly contribute to understanding how hardware-software co-optimization can unlock additional performance benefits in modern embedded and high-performance computing applications. This thesis provides hands-on experience with production-grade processor architectures, LLVM compiler development, performance analysis, and compiler optimization techniques.

Your Thesis Project

As part of your master's thesis, you will

• Analyze the microarchitectural characteristics of the RMX7xx, RHX1xx, and RPX1xx RISC-V processor families.
• Study processor pipelines, instruction scheduling, instruction fusion opportunities, and multi-issue execution behavior.
• Identify performance bottlenecks and opportunities for compiler-driven optimization.
• Design, implement, and validate new optimizations within the LLVM compiler framework.
• Evaluate the impact of compiler enhancements through benchmarking, profiling, and performance analysis.
• Collaborate with processor architects and software engineers to better understand hardware-software interactions.
• Document your findings and present recommendations for future compiler and processor improvements.

Required Qualifications

• Currently pursuing a Master's degree in Computer Engineering, Computer Science, Electrical Engineering, or a related field.
• Strong understanding of computer architecture and processor design concepts.
• Knowledge of compiler fundamentals, optimization techniques, and code generation.
• Experience programming in C/C++.
• Familiarity with Linux development environments and software development tools.
• Strong analytical and problem-solving skills.
• Ability to work independently while collaborating effectively with technical experts.
• Good written and verbal communication skills in English.

Preferred Qualifications

• Experience with LLVM or other compiler infrastructures.
• Knowledge of RISC-V architecture and instruction set concepts.
• Understanding of processor microarchitecture, pipelining, and performance optimization.
• Experience with benchmarking, profiling, or performance analysis tools.
• Exposure to embedded systems or low-level software development.

What You Will Gain

• Practical experience with state-of-the-art RISC-V processor technologies.
• Hands-on involvement in LLVM compiler development and optimization.
• Exposure to real-world hardware-software co-design challenges.
• Mentorship from experienced processor and compiler engineers.
• An opportunity to contribute to cutting-edge research and development in processor performance optimization.

If you are passionate about computer architecture, compiler technology, and performance engineering, we look forward to supporting your thesis journey in Leuven.

Information about our benefits you can find here: https://gf.com/careers/opportunities-in-europe/